Double edge triggered flip flop3/31/2024 This code assumes that the clock is fast enough to capture all the control signal pulses. I'm a lot more comfortable in verilog, so double check this VHDL (any comments appreciated). consider using a bank of 2 delays and using those outputsĮdge_flags: process (sig1, sig1_d1, sig2, sig2_d1) is If the contorl signals are not synchronous with clk, Flops to store a delayed version of the control signals Signal sig1_rise, sig2_rise : std_ulogic edges to control the state of an output variableĪrchitecture rtl of stackoverflow_edges is Finding edges of control signals and using the I'd then use these pulses to drive a tiny FSM to generate the 'bit' signal. What I'd usually do in this case is to keep a delayed version of both the control signals and generate a pulse one clock wide at the rising edge of each signal.
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